In many memory devices, including random access memory (RAM) devices, data is typically accessed by supplying an address to an array of memory cells and then reading data from the memory cells that reside at the supplied address. However, in content addressable memory (CAM) devices, data within a CAM array is not accessed by initially supplying an address, but rather by initially applying data (e.g., search words) to the array and then performing a search operation to identify one or more entries within the CAM array that contain data equivalent to the applied data and thereby represent a “match” condition. In this manner, data is accessed according to its content rather than its address. Upon completion of the search operation, the identified location(s) containing the equivalent data is typically encoded to provide an address (e.g., block address+row address within a block) at which the matching entry is located. If multiple matching entries are identified in response to the search operation, then local priority encoding operations may be performed to identify a location of a best or highest priority matching entry. Such priority encoding operations frequently utilize the relative physical locations of multiple matching entries within the CAM array to identify a highest priority matching entry. An exemplary CAM device that utilizes a priority encoder to identify a highest priority matching entry is disclosed in commonly assigned U.S. Pat. No. 6,370,613 to Diede et al., entitled “Content Addressable Memory with Longest Match Detect,” the disclosure of which is hereby incorporated herein by reference. Additional CAM devices are described in U.S. Pat. Nos. 5,706,224, 5,852,569 and 5,964,857 to Srinivasan et al. and in U.S. Pat. Nos. 6,101,116, 6,256,216, 6,128,207 and 6,262,907 to Lien et al., assigned to the present assignee, the disclosures of which are hereby incorporated herein by reference.
CAM cells are frequently configured as binary CAM cells that store only data bits (as “1” or “0” logic values) or as ternary CAM cells that store data bits and mask bits. As will be understood by those skilled in the art, when a mask bit within a ternary CAM cell is inactive (e.g., set to a logic 1 value), the ternary CAM cell may operate as a conventional binary CAM cell storing an “unmasked” data bit. When the mask bit is active (e.g., set to a logic 0 value), the ternary CAM cell is treated as storing a “don't care” (X) value, which means that all compare operations performed on the actively masked ternary CAM cell will result in a cell match condition. Thus, if a logic 0 data bit is applied to a ternary CAM cell storing an active mask bit and a logic 1 data bit, the compare operation will indicate a cell match condition. A cell match condition will also be indicated if a logic 1 data bit is applied to a ternary CAM cell storing an active mask bit and a logic 0 data bit. Accordingly, if a data word of length N, where N is an integer, is applied to a ternary CAM array having a plurality of entries therein of logical width N, then a compare operation will yield one or more match conditions whenever all the unmasked data bits of an entry in the ternary CAM array are identical to the corresponding data bits of the applied search word. This means that if the applied search word equals {1011}, the following entries will result in a match condition in a CAM comprising ternary CAM cells: {1011}, {X011}, {1X11}, {10X1}, {101X}, {XX11}, {1XX1}, . . . , {1XXX}, {XXXX}.
As illustrated by FIG. 1A, a conventional ternary CAM cell 10 may include a data SRAM cell 12, a mask SRAM cell 16, a compare circuit 14 and an NMOS transistor 18 that is electrically connected in series between the compare circuit 14 and a respective match line. As will be understood by those skilled in the art, data can be loaded into the data SRAM cell 12 by driving a pair of differential bit lines BIT and BITB with a rail-to-rail data signal (i.e., BIT=1, BITB=0 or BIT=0, BITB=1) and driving a respective main word line at an active high level. These driving operations will cause the outputs D and DB of the data SRAM cell 12 to remain at or switch to levels consistent with the value of the rail-to-rail data signal established on the respective pair of bit lines. An active mask value can be loaded into the mask SRAM cell 16 by driving the pair of differential bit lines BIT and BITB with a rail-to-rail mask signal that reflects a logic 0 value (i.e., BIT=0, BITB=1) and driving a respective mask word line at an active high level. These driving operations will cause the true and complementary outputs M and MB of the mask SRAM cell 16 to remain at or switch to logic 0 and logic 1 levels, respectively. As will be understood by those skilled in the art, setting M=1 will operate to turn on NMOS transistor 18 and cause the CAM cell 10 to operate as a conventional binary CAM cell. However, setting M=0 will operate to turn off NMOS transistor 18 and thereby preclude the compare circuit 14 from pulling down the match line to indicate a “miss” (i.e., inequality) between the bit of data stored within the data SRAM cell 12 and a bit of a comparand residing on the corresponding pair of differential data lines DATA and DATAB. In this latter case, the CAM cell 10 is treated as being actively masked and storing an “X” state, which represents a “don't care” condition. In some applications, the pair of differential bit lines and the pair of differential data lines may be electrically connected together as a single pair of bit/data lines.
A pair of ternary CAM cells 10′ may also share a respective mask SRAM cell 16′, as illustrated by FIG. 1B. Accordingly, setting the true output M of the mask SRAM cell 16′ to an active logic 0 value will operate to locally mask both upper and lower data SRAM cells 12 within the illustrated pair of CAM cells 10′ during each consecutive search operation. Groups of four (4) or (8) CAM cells within a respective column may also be locally masked by a shared mask cell that is located within the same column. Accordingly, whenever the shared mask cell is active during a search operation, local masking of all CAM cells within the corresponding group will be masked.
The aforementioned commonly assigned '613 patent to Diede et al. also discloses a segmented CAM array that is configured to perform pipelined search operations. Moreover, FIG. 7 of the '613 patent illustrates an external mask register that is used in combination with splitter logic to globally mask bits of an applied search word before multiple segments of the search word are supplied to pipeline registers associated with each segment of the CAM array.